Field of the Invention
The present invention relates to a method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. In addition, the invention relates to a method for calibrating an FPGA model. The invention also relates to a computer program product with computer-implemented instructions that executes the steps of the above method after loading and execution in a suitable data processing device. In addition, the invention relates to a digital storage medium with control signals that are read out electronically and that can interact with a programmable data processing device in such a manner that the above method is carried out on the data processing device.
Description of the Background Art
Real-time simulations of complex, dynamic models place high demands on even modern computing nodes due to the tight time constraints. In automotive hardware-in-the-loop simulations (HIL), such models are used primarily where fast control loops must be closed, for example for very dynamic parts of the environment model. This is the case, for instance, in the simulation of cylinder pressure sensors, which play an ever greater role in reducing fuel consumption and exhaust emissions. However, short cycle times and low latencies are indispensable for highly dynamic controlled systems as well, such as electric motors, for example. These are virtually impossible to achieve in practice now with CPU-based simulations. The field of Rapid Control Prototyping (RCP) represents another example. Field Programmable Gate Arrays (FPGA) are becoming increasingly dominant in such cases in order to continue to ensure sufficiently precise and rapid reaction times by the models. In this way, the simulated environment models (e.g., simulated electric motor) or the control units can be implemented reliably, for example in that complex controller components are moved out into the FPGA. Hence the simulated environment models can become ever more precise and complex.
FPGAs can support computing nodes in real-time simulation by taking over the calculation of dynamic components of a model. Even rigorous real-time demands can be met with ease through the use of FPGAs due to the high flexibility and the capability of parallel processing of signals. The FPGAs can serve as hardware accelerators for CPUs of computing nodes. For example, the DS5203-FPGA board from dSPACE represents one such extension for an HIL simulator. Accordingly, very dynamic components of the environment model are moved out into the FPGA, for example, so that sufficiently precise and fast reaction times continue to be ensured for the control unit. An FPGA hardware configuration is typically generated in a build process based on an FPGA model in a hardware description language.
Due to increasing requirements for precision, the models of controlled systems are becoming increasingly complex, and thus also difficult to manage. In the automotive HIL environment, such models are generally produced with the Matlab/Simulink tool set from The MathWorks Inc. Simulink offers a block-based view of such models in the form of a block diagram. Model components can be combined into subsystems in a block diagram, and connected to one another with signals. The flow of data between these blocks is represented by signal lines.
In a CPU-based real-time simulation, the block diagram of a model is first translated into C/C++ source files with the aid of the Simulink Coder. These files are then translated by a compiler into an executable application that can be executed on a computing node with a real-time-capable operating system. In addition, a trace file is produced during the CPU build, which represents a topology file with its graphical modeling, for example in Simulink.
The translation of a model into a CPU application has the result that the calculations of the simulation are executed sequentially, at a fixed step size. In this way, a consistent image of all model states or model variables, such as, e.g., data on the signal lines or input/output values of the blocks, is always present in the main memory of the computing node. As a result of the direct access to main memory, the model variables can be analyzed and/or manipulated at the runtime of the model in an experimentation tool such as, e.g., ControlDesk. Random read/write access to variables of the HIL simulation is possible. Using the trace file, signal values such as engine speed can be selected and output or manipulated through a display. In the HIL environment, this procedure is summarized under the terms “measurement” and “adjustment.”
An FPGA-based simulation can be modeled in a block diagram with Simulink with the aid of the Xilinx System Generator (XSG) and the FPGA Programming Blockset from dSPACE, in a manner analogous to CPU-based simulation.
In contrast to CPU simulation, however, this model is not translated into an iterative programming language, but instead into a hardware description language that describes a customer-specific digital circuit. The description of the customer-specific digital circuit is translated into an FPGA configuration data stream by a synthesis process. Thus no option exists for adjusting signals that have been placed on the FPGA. Consequently, a method that saves resources and time is desirable, particularly in the area of control unit calibration, in which a great many parameters must be set.
Calibration data are customarily modeled and implemented as constants, so modifications typically cannot be made at the runtime of the FPGA. This is entirely desirable for a final model, for example a release version or standard version, since the implementation of constants in FPGAs can be achieved simply and with few resources. Nonetheless, the process of calibration and debugging is made more difficult by the constants, since changing the signal values of the constants necessitates the generation of new FPGA code each time. A different modeling of the constants as variables could solve this problem with regard to modifying the signal values. Disadvantages with respect to the performance of the FPGA model as well as the utilization of resources ensue here, however, because of the implementation of the variables with modifiable values as FPGA code. Different implementations, for example an FPGA model using variables with modifiable values for calibration and debugging, and an FPGA model using constants with static signal values for the release, entail the disadvantage that the FPGA model must be changed for the transition to release, which is error-prone. Moreover, differences with regard to performance may result from the different modeling, with the result that errors may at times go undetected or may not occur until release of the FPGA code.